# Verilog and SystemVerilog Cheat Sheet for Sim and Synthesis

Source: https://srvscripts.com/guides/verilog-cheat-sheet/
Updated: 2026-10-09
Publisher: srvScripts (https://srvscripts.com/)

**Short answer:** Verilog describes hardware: `assign` and `always @*` model combinational logic, `always @(posedge clk)` with non-blocking `<=` models flip-flops, and `initial` blocks with `#` delays belong in testbenches only. SystemVerilog (IEEE 1800-2023) adds `logic`, `always_ff`, `always_comb`, `typedef enum` for state machines, packed structs, packages, interfaces and assertions. Simulate with Icarus Verilog or Verilator, lint with `verilator --lint-only -Wall`, and synthesise with Yosys or your FPGA vendor’s tools.

The examples in this Verilog cheat sheet were simulated with Icarus Verilog 12.0, linted with Verilator 5.020 and synthesised with Yosys 0.33 on 9 October 2026. Support for SystemVerilog differs between tools; the notes say where Icarus 12 refused a construct.

## Module structure and ports

```
`timescale 1ns/1ps
module counter #(
    parameter WIDTH = 8
) (
    input  wire             clk,
    input  wire             rst_n,      // active-low reset
    input  wire             en,
    output reg  [WIDTH-1:0] count,
    output wire             wrap
);
    assign wrap = en && (count == {WIDTH{1'b1}});

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)  count  busy); | Concurrent assertion: |=> checks the next cycle (Verilator linted it; Icarus 12 rejected the syntax) |

## Simulate, lint and synthesise with open-source tools

| Command | What it does |
| --- | --- |
| iverilog -g2005 -Wall -o sim counter.v tb_counter.v | Compile Verilog-2005 with Icarus |
| iverilog -g2012 -o sim tx_fsm.sv tb_tx.sv | Compile with SystemVerilog support enabled |
| vvp sim | Run the compiled simulation |
| verilator --lint-only -Wall tx_fsm.sv | Strict lint: widths, latches, unused signals, file names |
| verilator --binary -j 0 tb.sv dut.sv | Build a fast C++ simulation (needs a C++ compiler; slower to build than Icarus) |
| yosys -p "read_verilog -sv tx_fsm.sv; synth -top tx_fsm; stat" | Generic synthesis and a cell count |
| gtkwave tb_tx.vcd | View waveforms |

**For server admins:** the tools install from the distribution packages (`apt install iverilog verilator yosys` on Debian and Ubuntu), and a lint plus simulation run fits in a CI job: fail the build if `verilator --lint-only -Wall` returns non-zero or the testbench prints no `PASS` line. Silence single Verilator warnings with options such as `-Wno-DECLFILENAME` rather than dropping `-Wall`.

**Official documentation (checked 9 October 2026):** [IEEE 1800-2023 SystemVerilog standard](https://standards.ieee.org/ieee/1800/7743/) · [IEEE 1364-2005 Verilog standard](https://standards.ieee.org/ieee/1364/3641/) · [Icarus Verilog documentation](https://steveicarus.github.io/iverilog/) · [Verilator user guide](https://verilator.org/guide/latest/) · [Yosys documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/)

## Verilog Cheat Sheet at a glance

In short: A compact Verilog and SystemVerilog reference for writing synthesisable RTL and simple testbenches, with the open-source commands to simulate, lint and synthesise.

Verilog Cheat Sheet: what this guide covers.

**Related:** [C Cheat Sheet: C17 and C23 Syntax, Memory and gcc Flags](https://srvscripts.com/guides/c-cheat-sheet/) · [C++ Cheat Sheet: C++20 and C++23 Syntax, STL and Ranges](https://srvscripts.com/guides/cpp-cheat-sheet/) · [Number Base Converter](https://srvscripts.com/tools/number-base-converter/).